(1) Field of the Invention
The present invention relates to a data processing unit, and more particularly, the invention relates to a data processing unit which controls the temporary storage, error correction, and data transfer after correction of the demodulated data read out and sent from a storage medium, such as a CD-ROM, a music CD, or a DVD-ROM made in conformity to the CD format or the DVD format.
(2) Description of the Prior Art
(General Background Art)
The reading double speed of a DVD-ROM drive or a CD-ROM drive has recently made a great progress. As a result, there is an increasing demand for improvement of performance of the data processing unit used for decryption and error correcting signal processing of DVD format and CD format.
FIG. 1 illustrates a general configuration of a data processing unit such as this. In FIG. 1, 1 represents a demodulating circuit which demodulates the physical data read out from an optical disk medium; 2, a buffer memory serving as a buffer which temporarily stores the demodulated data sent out from the demodulating circuit for error correction and transfer to the outside (hereinafter simply referred to as the xe2x80x9cmemoryxe2x80x9d or the xe2x80x9cstorage meansxe2x80x9d); 3, an error correcting circuit which performs error detection by reading out the data stored in the memory, correcting the detected errors, and then writing back the corrected data again into the buffer memory 2; 4, an external interface circuit which reads out the corrected data from the buffer memory 2 and outputs the same to an external host PC, an SCSI (small-sized computer interface), or an interface LSI with a standard external bus such as 1394, a kind of i/f specifications; 5, a bus control circuit which controls the data transfer between a peripheral circuit such as the demodulating circuit 1, the error correcting circuit 3, or the external interface circuit 4 and the buffer memory 2; and 6, a command processing circuit which teaches the details of command to the above-mentioned components by receiving a command from the outside. (Operation of this circuit will be described later in details under the heading of xe2x80x9cThe Preferred Embodimentsxe2x80x9d).
An actual data processing unit has other components such as a wobble signal detection circuit, in addition to the above, and furthermore, the error correcting circuit has a syndrome operator, resulting in a far more complicated structure, however, since these other components do not have a direct relationship with the intent of the present invention, the illustration are explanation thereof are omitted here.
The buffer memory 2 is overwritable, and the data 100 read out first are demodulated by the demodulating circuit 1, and is rewritten into the correct data as a result of the correction performed on each plural numbers of error correction by the error correction circuit 3 according to necessity. In FIG. 1, 100 and 101 represent the signal lines into which data are entered in a more accurate sense of work, however, because such an accurate expression each time might often lead to complications, and rather a simpler representation would not cause any misunderstanding, this shall also apply hereafter in this specification. And, this is also the case with other signals and pieces of the information (or lines thereof) appearing hereafter.
The reading double speed of DVD-ROM drive or CD ROM drive, i.e., the rotating speed of the optical disk is dependent upon the bus band width of this (buffer) memory. This memory generally comprises an SRAM (static random access memory) or a DRAM (dynamic random access memory) as illustrated, however, because it also serves as a cache memory for external output, it becomes necessary to provide a larger capacity, the higher the transfer rate with the outside becomes. Because of this, memory having a high recording density and available at a low cost such as a DRAM is used in many cases.
On the other hand, however, the access speed of a DRAM is lower than that of an SRAM, thereby causing a problem in the performance. Particularly, the data demodulated in the demodulating circuit are divided into usual user""s data, error correcting data, and other additional information, and are written separately into the predetermined areas (address spaces) in the memory for each kind of the data. However, because data are not transferred in a predetermined sequence from the demodulating circuit, or may not be transferred at all, the execution of writing into the DRAM will be executed every time the data are transferred as a result, and therefore the high-speed access mode (page mode) of DRAM is not applicable.
(Background art having a particularly close relationship with the problems to be solved by the invention)
Accordingly, in a data processing unit as described above, the bus band width of the memory which temporarily stores the demodulated data for the purpose of error correction and transfer to the outside forms a bottleneck for the system processing performance.
Then, in order to write the demodulated data into the memory as efficiently as possible, it is proposed, for example, to provide a circuit or a memory which temporarily stores demodulated data as divided in terms of the kind of the data in the bus control circuit, and write the data for each kind of the data into the memory by use of the high-speed access mode. This practice may certainly contribute to a higher write efficiency, but will cause an increase in the hardware.
Because of this, there has been an increasing demand for the achievement of a data processing unit permitting efficient write of demodulated data into the memory by addition of only a slight amount of the hardware.
The present invention was developed in view of the problems as described above, and in the invention, the demodulated data of the same kind are written into a storage means simultaneously, or are written continuously in the transferred sequence, because the data of the same kind are stored in an area within the storage means, and particularly, the continuous data within the same kind are stored in principle in continuous addresses. For this purpose, firstly, a special communication line is provided so that the bus control circuit can recognize the kind of the demodulated data being sent in next in addition to the current modulated data. Secondly, the access requests to the storage means are also adjusted. More specifically, the details are described as follows.
In the first aspect of the invention, the demodulating means sends the data read out from the optical disk and demodulated to the bus control means for the time being in order to store into the storage means for the purpose of error correction or for using as a buffer upon transferring the same to the outside. And, in this occasion, the kind of the data to be demodulated and sent in next is also sent by use of a signal line. The kind of the data is recognized from the number of the data, the signal line, the top code of the sector, the rules of the data storage, etc.
The bus control means temporarily stores the demodulated data currently being sent, the kind of the demodulated data to be sent next, and the information specifying the same in a temporary built-in storage sub-means. When the next data kind information sent in accordance with the first demodulated data is different from a data kind of the first demodulated data currently being sent, the write control sub-means issues a request such that only the first demodulated data be written in the storage means, the write request of the first demodulated data being issued at a good timing.
The expression xe2x80x9cissued at a good timingxe2x80x9d means issuing a write request promptly, taking account of the time required for the bus control means to adjust write requests from various components, if there is no write request into the storage means of a higher priority, so that the demodulated data having already arrived and currently being sent can be written in the sequence of arrival without waiting for the arrival of all these data, or promptly without delay or as soon as possible after arrival of all the data.
Further, the expression xe2x80x9cissuing a write request promptlyxe2x80x9d means accessing and writing, immediately or after arrival of all the data (a slight delay may actually occur, depending upon the clock signal or the system), upon receipt of a write enable (agree, OK) signal, the demodulated data already stored in the temporary storage sub-means at the time of receipt of the signal, or the demodulated data being sent at the time of receipt of the signal, if any.
On the other hand, if the data kinds are the same, a write request is issued at a good timing, requesting to continuously write first demodulated data being stored or having already been stored in the temporary storage sub-means and demodulated data sent immediately after the first demodulated data or to be sent, in a single access, into an area of the storage means dependent upon kind of the data, at the latest within a prescribed period of time after arrival of the next demodulated data (at least the top thereof), and these data are promptly and continuously written when the request is accepted.
This is also the case with xe2x80x9cissuing a write request at a good timingxe2x80x9d as same as the above.
In principle, therefore, the data are first written in the prescribed area for the data in the temporary storage sub-means, and then, the following demodulated data are written, via the temporary storage sub-means, or directly (depending upon hardware or software adopted for the unit) into the next address in the same area.
It is needless to mention that if write or read of the other data is conducted upon occurrence of the write request of the demodulated data, writing of the demodulated data must wait for the completion of such processing, or if another access request is made, adjustment is performed with the request in accordance with the priority.
It is also needless to mention that unnecessary information written in the temporary storage sub-means such as the data kind of the demodulated data and the next demodulated data stored simultaneously and the data kind of the demodulated data currently being written is erased, or eliminated by overwrite of the following demodulated data.
The data output to outside are not limited to data free from error and not covered by correction (this may not be the case with CPU programs or data for arithmetic operation) or data of which correction has fully completed, but include of course data to be processed later because of the impossibility to correct or data of which correction has been completed for the time being.
Furthermore, even within the storage means, unnecessary data such as demodulated data containing errors or demodulated data already transferred are eliminated by overwrite of corrected data or following demodulated data, or intentionally erased.
In a second aspect of the invention, the temporary storage cub-means is FIFO. It is therefore convenient when continuously transferring demodulated data of the same kind to the storage means.
It is also needless to say that the data kind of the demodulated data currently being stored may similarly be stored in FIFO, or in a separate memory.
In a third aspect of the invention, there are provided two FIFOs for continuous write of two continuous demodulated data of the same data kind in a single access as the temporary storage sub-means. When continuously writing the two demodulated data of the same data kind into the storage means, a high speed is achieved by using theses two FIFOs.
It is needless to mention that, when the data kind of the demodulated data in the first FIFO differs from that of the demodulated data to be transferred next, a request is issued to write the demodulated data in the first FIFO into the storage means. If the next demodulated data are transferred during write or during standby, storing thereof into the second FIFO may be carried out.
In a fourth aspect, many FIFO are provided, which stores the kind of demodulated data sent next, in addition to a set of the demodulated data sent to the buffer in the bus control means when temporarily storing the demodulated data into the storage means. These FIFOs are not of a strict serial type. As a result, it is possible to write, read out or output by skipping the data in some cases independently of the other FIFOs. That is, this is a bundle of FIFOs. If a prescribed number; for example two, demodulated data of the same kind are stored in these FIFOs, or stored when taking account of the demodulated data next to those currently being sent, these demodulated data of the same kind are continuously written, in a single access, in a prescribed area in the storage means (in the sequence of arrival in principle) (It is therefore possible to continuously write the already stored demodulated data and demodulated data currently being sent, making a total of two, as well as the demodulated data to be sent next, making a total or three, or the demodulated data already stored and the demodulated data to be sent next, making a total of two. This may of course be only two, depending upon the hardware or software configuration).
When the number of empty FIFOs is smaller than a prescribed value, a write request to write starting from the demodulated data having arrived first in principle into the storage means is issued, and immediately upon the bus becoming available, write into an area dependent upon the kind of the demodulated data is started.
A function of completing the write into the storage means as soon as possible by storing data of the same kind into continuously arrange FIFOs may of course be added.
The means for recognizing an empty FIFO, the means for specifying FIFOs to store the demodulated data, and the means for specifying FIFOs for the output and output sequence are directly or indirectly provided.
In a fifth aspect of the invention, the prescribed number described as to the fourth aspect is two. Data of the same kind are accessed in units of two, and continuous write is performed. The certain number of empty FIFOs for which a write request is issued when data of the same kind are not present, varying with the frequency of error correction or outside transfer, the necessary machine cycle and the frequency of transfer of the demodulated data, usually suffices to be one.
In a sixth aspect of the invention, there are provided FIFO in a number of data kinds +1. There is therefore available an increase in probability of continuous write of demodulated data of the same kind into the storage means into a prescribed area in a single access.
In a seventh aspect of the invention, the number of kinds of data to be demodulated is three, and the number of FIFOs is four.
In an eight aspect of the invention, if demodulated data of the same kind as the demodulated data currently being written into the storage means are sent from the demodulating means to the bus control means, such data are also written continuously.
In a ninth aspect of the invention, write of the demodulated data into continuous addresses to the storage means (conceptually) comprises only movement to the next address (present at the top and bottom or right and left) of write means (arm). The necessity to move to a distant write address is therefore eliminated. It is therefore possible to conduct data write in a high speed mode.
In a tenth aspect of the invention, although similar to the fourth aspect the FIFOs store only the demodulated data. The data kind of the demodulated data is separately stored, and the data kind of the demodulated data sent next, which is used for determination for only a single access, is not stored for a long period of time.